Signal integrity to be addressed at wafer conference

Signal integrity for wafer-level test will be highlighted at the upcoming International Wafer-Level Packaging Conference and Tabletop Exhibition, October 27-30, in Santa Clara. Jason Mroczkowski, RF engineering and product manager at Everett Charles Technologies, will hold a presentation titled “Signal Integrity Simulation of the Wafer Test Environment” Friday October 30 at 3 p.m. He will describe how to help ensure the optimum performance of wafer-test hardware prior to manufacturing, thus minimizing time to market and cost of test. He will recommend signal-integrity simulation to provide confidence that the electrical performance of the test environment matches the requirements of the device under test. He’ll note that simulation can eliminate extensive lab testing and allow a direct path from fabrication to production.

Mroczkowski’s presentation will provide a description of a full test-interface path and discuss the simulation techniques used to capture each structure within that path. He will also discuss the structures and interfaces that must be captured in simulation to ensure the results match actual measurements. In addition, he will cover optimization and the multiple areas of focus to help determine which optimization will have the largest impact.

Finally, Mroczkowski will conclude by showing a sample simulation including a device model, package model, wafer-probe model, and PCB layout model, all within one simulation environment. He will explain how simulation and optimization methods previously described are used to meet device requirements for a specific wafer-test application.

For more on wafer test, see “Cascade addresses high-frequency test, studies TSVs and other emerging technologies.”

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