Atrenta hosts 3-D SoC design flow demo

ANAHEIM, CA. An effective EDA flow for 3-D chip design will become critical for the development and production of optimized stacked-die chip systems. Atrenta, AutoESL, Qualcomm, and IMEC have been collaborating on 3-D chip design, and they demonstrated what might be called a working prototype front-end 3-D chip design system June 14 at the Design Automation Conference at Atrenta’s booth.

The flow the companies demonstrated addresses 3-D-aware high-level synthesis, early partitioning, floorplanning, and multi-domain analysis. Commenting on the first of these elements, Atul Sharan, president and CEO of AutoESL, said, “The daunting challenges of 3-D design demand a 3-D-aware high-level synthesis approach.” Commenting on the other elements, Ravi Varadarajan, Atrenta fellow, said, “Early partitioning, floorplanning, and analysis yields substantial benefits for design predictability on conventional advanced SoCs. With the emergence of 3-D multi-technology design, this activity now becomes an absolute must-have. You simply cannot hand off a 3-D design to back-end implementation without knowing for certain that it’s partitioned correctly.”

The demonstration grew out of what Riko Radojcic called PathFinding technology, which Qualcomm has been developing over a number of years. Radojcic said that with traditional Moore’s law process migration—from 90 to 65 nm, for example—it’s relatively easy to project what will happen. The new geometry will yield devices that are smaller, faster, and leakier—information that can assist in building working and yielding parts.

Such projections aren’t necessarily valid or helpful with 3-D parts. What’s needed, Radojcic said, is something that allows you to explore knobs at both the architectural and process end, adding, “That’s PathFinding to me.” The collaboration with Atrenta, AutoESL, and IMEC, he said, is an effort to build a commercial set of tools that assist the PathFinding function. He said some might question how accurate such tools might be, but he called that the wrong question. The issue isn’t accuracy with respect to a final design but rather how effective it would be with respect to current, spread-sheet-based methodologies. The goal, he said, is an effective set of tools to help explore the many degrees of freedom that stem from the die-to-die proximity of 3-D chip stacks—not to eliminate the need for testchips and other process-validation technologies.

Pol Marchal, principal scientist for IMEC’s 3-D SoC design initiative, who assisted with the June 14 demonstration, had addressed PathFinding technology June 8 at the IMEC Technology Forum at the organization’s headquarters in Leuven, Belgium. IMEC’s overall 3-D efforts, he said, involve investigations of TSV (through-silicon-via) technology, wafer thinning and backside processing, the packaging of 3-D die stacks, cost modeling, and 3-D system exploration, with the last being germane to PathFinding technology.

Marchal called PathFinding a systematic exploration of tradeoffs. “Understanding the system requirements provides the engineer with inputs to guide design and technology decisions,” he said, adding that a PathFinding flow allows engineers to iterate on design and technology choices to optimize footprint, timing, thermal performance, and other functions. He cited as an example a mobile-consumer device, which would require three or four chip tiers with a package thickness of less than 0.6 mm, more than a thousand TSVs per tier operating at 400 MHz and providing a 12.8-Gbyte/s data rate, all while consuming less than 2.5 pJ/bit. PathFinding analysis, he said, shows the feasibility of building such a device.