UNH-IOL Test Fixture Overview: MIPI TLIS Board

In our previous post, we talked about issues experienced when using FR4 material in PCB. This week, we’ll discuss some of our other test fixtures that are used to perform testing here at the lab. All of our test fixtures are designed and populated in-house, and we use Altium Designer, a powerful all-in-one program for schematic capture and PCB layout. Today, we’ll delve into the MIPI TLIS board and later this week, we’ll take a look at the Passive Line Tap board used for examining signals in twisted pair Ethernet.

The MIPI (Mobile Industry Processor Interface) D-PHY Transmission-Line Interconnect Structure (TLIS) board is used for MIPI interoperability testing, which was designed to provide a sufficient insertion loss to meet the Sdd12 and Sdd21 template in the MIPI-DPHY Spec. Since the signaling for MIPI D-PHY is in the sub-gigabit range, the loss from FR4 would be minimal and the traces would have to be extremely long in order to provide enough loss to meet the specifications in the standard. To keep the board area small and keep costs at a minimum, we use 5.5-inch long traces and a 10-inch micro-coax flex cable to provide an insertion loss that meets the requirements. The TLIS board is shown in the picture below. In the second picture we have the insertion loss plot of the board where the blue lines denote the differential insertion loss of a single lane (Clock lane) of the TLIS board and the light blue shading is the insertion loss template from the D-PHY Spec.

MIPI D-PHY TLIS v1 Board

Insertion Loss for CLK Lane

Check back later this week for our post on the Passive Line Tap test fixture, which was designed to observe and measure bi-directional traffic being sent over a differential pair for 1000BASE-T and 10GBASE-T environments with minimal interference to the signal.

Michael DeGaetano, Research and Development