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Memory Test
Testing memory is proving to be a big hassle for many designers, as buses become more complex and the standard methods of memory test no longer apply. The good news is that new approaches are evolving to test memory, and this critical area of test may not be quite the ordeal it once was. This collection contains articles and information that aims to help you on your quest to simplify memory test.
How to test high-speed memory with non-intrusive embedded instruments, part 3
- 10.09.2012
Non-intrusive memory test methods deliver high visibility and test coverage Read More...
Achieve Lower Silicon Cost Using Embedded Memory Test and Repair
- 09.19.2012
In this webinar, we will discuss advanced embedded memory test solution capabilities including hierarchical implementation and validation, fault detection in very deep submicron technologies, repair at the manufacturing level, diagnosis for process improvement and field repair and error correction (ECC) capabilities that address today's design yield and reliability needs. Read More...
Thorough test means testing through the RAM
- 09.17.2012
It is easy to miss testing for timing defects between memories and logic. Read More...
Memory Flaws Boot Camp
- 09.14.2012
- 2 comment(s)
Based on the top memory weaknesses identified by CWE, this no-charge eLearning course will describe the cause and security impact of these flaws, provide technical examples of each and offer strategies to help mitigate the risks they pose. Read More...
How to test high-speed memory with non-intrusive embedded instruments, Part 2
- 09.13.2012
A review of non-intrusive debug and test methods based on embedded instruments and how these methods can meet the challenges that design and manufacturing engineers are encountering. Read More...
How to test high-speed memory with non-intrusive embedded instruments, Part 1
- 09.04.2012
- 1 comment(s)
Part 1: The problem with memory test Read More...
Memory testers expand embedded instrument library
- 08.11.2012
Two memory test instruments join Asset InterTech’s ScanWorks embedded instrumentation library for its FCT (FPGA-controlled test) circuit-board test tool, giving engineers a nonintrusive means of increasing test coverage. Read More...
Viewpoint: Memory BIST for shared-bus applications
- 02.16.2012
Shared-bus memory BIST has a special structure because it doesn’t interface directly to the memories it is testing. Read More...
Mentor Graphics and ARM team up on memory test and repair
- 11.06.2010
A new capability provides interoperability between Mentor's Tessent memory test and repair product and ARM's family of cores and embedded memory IP. Read More...
Verigy introduces redundancy analysis option for its V6000 WS memory test system
- 07.01.2009
The scalable SmartRA allows manufacturers to meet the expanding fail-storage and performance requirements of redundancy analysis for DRAM. Read More...
