PCB test: nails or TAP?
Rick Nelson, Senior Technical Editor- September 1, 2002
In-circuit test (ICT) systems have been the leaders in using electrical means to look for structural defects in PCBs. They employ bed-of-nails fixtures to provide electrical access to as many as 7000 or so circuit nodes simultaneously. But with the prevalence of multilayer boards and ball-grid-array (BGA) packages, circuit access isn't what it was in the era of single-sided PCBs populated by dual in-line packages (DIPs) and discrete components. To make up for the lack of physical access to electrical test points, boundary scan has emerged to provide access to nodes not accessible to fixture nails. In addition, it offers a fixtureless test alternative even when access is available.
Boundary scan was first proposed in 1985 and became the IEEE 1149.1 standard in 1990. But it has been slow to catch on, because it requires that IC manufacturers produce devices compatible with the boundary-scan spec (Ref. 1). Each device must physically include the standard-defined 4-wire Test Access Port (TAP), internal boundary-scan cells for each pin, and associated internal boundary-scan registers and other circuitry. In addition, the device vendor must provide Boundary Scan Description Language (BSDL) files that describe the workings of the chip's boundary-scan functions. That once meant a complexity that IC manufacturers were unwilling to fabricate and chip costs that customers were unwilling to pay. Gradually, however, PCB test-point-access problems proved to be more formidable than the problem of fabricating cost-effective boundary-scan-compliant digital devices, and board designers now can select from a variety of boundary-scan-compliant devices to populate their boards (Ref. 2).
Even when designers began including boundary-scan-compliant devices on PCBs, test engineers were seldom able to make full use of boundary scan's promise. That's because, says Harry Bleeker, managing director of JTAG Technologies, classic ATE companies made use of the technique only to improve the quality of ICT, delivering boundary-scan vectors via the bed-of-nails—a technique called boundary in-circuit test (BICT)—but not supplanting the requirement for bed-of-nails access.
BICT's goal was to speed test-program development. In the early 1990s, notes Glenn Woppman, president, CEO, and founder of ASSET InterTech, test engineers might require weeks to develop an ICT strategy for a complex part like an Intel '386 microprocessor. For a boundary-scan-compliant version of the same device, test-development times could shrink to hours. At the time, neither board designers nor ATE vendors pushed for a comprehensive boundary-scan-based test strategy, says Woppman, so designers didn't complete the scan chains from device to device.
With this approach, ATE vendors treated each compliant component or judiciously designed cluster of compliant and non-compliant components (Ref. 3) as an isolated boundary-scan island. That worked when 90% to 100% of test nodes were accessible to a bed of nails. But bed-of-nails coverage is shrinking—Woppman estimates that on average 50% of a board's nodes are accessible via nails today, and the figure will shrink to only 10% by 2005.
To deal with limited access, designers are connecting the scan chains and making the scan signals available through low-cost connectors. Those connectors open the door for board test to be performed by low-cost boundary-scan test hardware and software from companies including Acculogic, ASSET InterTech, Corelis, Goepel Electronics, Intellitech, and JTAG Technologies.
Figure 1 illustrates how a bed of nails and a TAP connector can deliver boundary-scan test vectors. The TAP itself includes four signals: Test Data In (TDI), Test Mode Select (TMS), Clock (CLK), and Test Data Out (TDO); some implementations include a reset signal as well. These signals control the states of boundary-scan cells (shown in yellow), with one cell assigned to each device I/O pin. During normal operation, these cells connect I/O pins to device internal circuitry.
|Figure 1. Boundary scan can make use of ICT nails to deliver test signals to PCB-mounted components such as the one on the left. Ball-grid-array packages such as the one shown on the right require that the signals be delivered via PCB traces and a Test Access Port connector (bottom).|
Asserting the TMS signal causes the cells, configured as a serial shift register, to carry test data, which shifts into and out of the device via the TDI and TDO lines at one bit per clock cycle. The interconnected scan-cell registers of multiple interconnected devices form a scan chain; PCBs populated with boundary-scan devices may have several scan chains or, as Woppman has noted, none.
If a PCB has no scan chains, then you must use BICT to perform boundary-scan tests on boundary-scan-compliant devices. To test IC1 in Figure 1 using BICT, nails contact each device solder pad (shown in gray). With the test mode selected, test data values residing on each device I/O pin (blue), shifted into and out of the device using the TDI and TDO signals, should equal the values measured by the nails contacting the corresponding solder pads. Data mismatches indicate bad solder joints.
BICT won't work for IC2, though, whose solder balls are hidden under its ball-grid-array package. You can, however, transfer test signals to and from IC2's I/O pins by means of the TAP—if your PCB designer routed the TAP signals to an external connector (the green wires in Figure 1) to complete a scan chain. In that case, a boundary-scan test controller can shift test data from the TAP connector into IC1. The sequential test-data will begin appearing at output A after nine clock cycles. That pattern should simultaneously appear at IC2 input B and its associated scan cell. External test hardware can verify that pattern, which will begin appearing at TDO 10 clock cycles later. If the expected pattern doesn't appear, then the solder joint at A, the solder joint at B, the trace connecting them, or either device's internal scan circuitry is defective.
A boundary-scan-compliant board, therefore, seems to present you with two test approaches: You could employ a bed-of-nails fixture costing thousands of dollars plus an ICT ATE system costing tens of thousands of dollars, or you could employ a boundary-scan controller card costing a few hundred dollars plus a TAP connector costing maybe a few cents.
No clear winner
The choice is less clear-cut than you might think. Not surprisingly, ICT ATE powerhouses Agilent Technologies and Teradyne predict a symbiotic future for boundary scan and ICT, with the techniques performing complementary functions within ever-denser PCBs.
Boundary-scan companies differ in their opinions, which range from the belief that boundary-scan test will operate autonomously of ICT (if not supersede it) to an "if you can't beat them, join them" approach that forecasts an ongoing major role for ICT in performing boundary-scan test. The latter is exemplified by an alliance announced last fall between Agilent and boundary-scan vendor ASSET InterTech and by the efforts of boundary-scan-system maker Acculogic, which, says president Saeed Taheri, derives 30 to 40% of its revenue by developing test strategies for third-party ICT systems. The role of autonomous boundary-scan test is embodied in an approach championed by Intellitech, which employs embedded test to execute digital tests independent of ICT platforms, which will continue to provide simple manufacturing-defect analysis and analog test. With the exception of an IC developed by LogicVision and National Semiconductor (Ref. 4), analog circuitry has not been amenable to boundary-scan test, despite the IEEE's approval of the 1149.4 analog extension to the original 1149.1 digital standard.
Intellitech's president, C.J. Clark, elaborates on his company's reasoning: "Digital test and logic-configuration times are increasing, and if a boundary-scan-testable PCB's digital-test and configuration time is long relative to its analog-test and handling time, it doesn't make sense to run digital tests on the ICT." He explains that if boundary-scan test, including FPGA, CPLD, and flash configuration (Ref. 5), takes 100 s and analog test takes 5 s, an ICT-only approach would provide a throughput of one PCB per 105 s.
The better alternative, he says, is to embed boundary-scan-test capability within the PCB itself so that execution of the boundary-scan test requires nothing more than a power supply. With this approach, the 5-s analog test runs on the ICT; the PCB is then removed from the ICT fixture and powered with other PCBs going through the boundary-scan self-test process.
After the first 20 PCBs have undergone analog testing (20 x 5 s), the first PCB will have completed its digital boundary-scan self-test and configuration. Within another 5 s, the second PCB undergoing digital boundary-scan self-test will have completed its test, and so on. After test of the first 20 PCBs, embedded test and configuration cancels out the digital test times, and the PCB throughput becomes one PCB per 5 s, the time it takes for analog test and handling.
To enable implementation of this alternative, Intellitech in June introduced its patent-pending SystemBIST configuration and test processor, which embeds self-test functions as well as in-system configuration of FPGAs and CPLDs within single PCBs or within multiple-PCB systems. Clark explains that the fully embedded test functionality that the SystemBIST processor provides can be used throughout a device life cycle, providing diagnostic information during prototyping, during accelerated life-cycle tests, and during high-volume production.
The SystemBIST processor is compatible with any device compliant with the IEEE 1149.1 or IEEE 1532 standard (Ref. 6) and can replace the electrically alterable configuration PROMs typically used for loading configuration data at power-up. A SystemBIST processor packaged in a 144-pin TQFP IC requires only half the PCB real estate of the PROM-based alternative, Clark said. SystemBIST functionality is also available as VHDL or Verilog intellectual property.
ICT delivers scan vectors
Others contend that an in-circuit tester remains a viable vehicle for delivering boundary-scan signals. It was in an effort to exploit ICT's advantages that ASSET InterTech and Agilent Technologies announced their agreement last fall. Woppman of ASSET InterTech might tacitly agree with Clark on boundary scan's value independent of ICT, but he jokes that he has waited a dozen years for ICT to go away, and he doesn't plan to wait another dozen years. More seriously, he sees ICT users as risk-averse types unlikely to replace their current test strategies with a predominately boundary-scan one.
An evolutionary approach might ease the fears of such types. Acculogic's Taheri sees a gradual increase in boundary-scan's importance within ICT while ICT's value diminishes over time. Ultimately, he sees boundary-scan power-up tests combined with flying-probe or functional tests (which he defines as test access via an edge connector or board connector—not via a bed of nails) as becoming mainstream PCB test techniques that provide the fault coverage and diagnostic resolution now available from ICT. In pursuit of these goals, Acculogic has developed an adaptive-clocking scheme that permits the delivery of boundary-scan signals over the several meters of cable required for a flying prober or for a functional test that takes place within an environmental chamber.
Menachem Blasberg, president of Corelis, already sees customers forgoing ICT—he says they perform boundary-scan test and then follow up with a thorough functional test to ensure proper real-time digital and analog performance. Acculogic's Taheri goes a step further, defining boundary scan as a test executive that establishes appropriate internal PCB logic states to facilitate analog functional tests.
The debate over ICT is made more complicated by the increasing reliance on contract manufacturers (CMs) for test services. Intellitech's Clark says he believes CMs resist boundary scan because they want to sell time on their installed ICT systems. Bleeker of JTAG Technologies notes, however, that smart CM customers are beginning to prescribe boundary-scan tests in an effort to lower costs, and the CMs must listen. An all-ICT approach, he says, is reserved for customers who haven't designed in boundary-scan compliance.
|Figure 2. Boundary scan and in-circuit test work together in a melding of Agilent Technologies’ 3070 in-circuit tester and ASSET InterTech’s ScanWorks boundary-scan software. Courtesy of ASSET InterTech.|
But even with boundary-scan designs proliferating, ASSET InterTech's Woppman sees a continuing role for ICT hardware. He credits ICT makers with having mastered high-volume production-test skills such as automated board handling and repair-ticket generation. He believes that boundary scan can enhance instead of replace current ICT strategies, and to that end, his company has adapted its ScanWorks boundary-scan software to work seamlessly within Agilent's 3070 Series in-circuit testers (Figure 2).
Barry Odbert, product manager at Agilent Technologies' Manufacturing Test Division, points out some benefits of ICT that boundary scan alone can't offer. For example, he cites vectorless test techniques such as Agilent's TestJet technology, which measures capacitance between a DUT metal lead frame and an external plate. Smaller-than-expected capacitance values can indicate poor solder joints. And if, for example, a scan chain is broken at the point indicated by the red X in Figure 1, a boundary-scan tester can tell you only that the chain is broken, whereas strategically placed nails can physically locate the defect for you.
Alan Albee, software products manager at Teradyne, cited several benefits of a combined ICT and boundary-scan approach at last year's International Test Conference (Ref. 7): ICT driver/sensor circuits can test non-scan devices and then condition them so they don't interfere with subsequent boundary-scan tests; a test combining ICT and boundary-scan test is more tolerant of BSDL errors than is boundary scan alone; and ICT drivers can control slew rates and voltage levels of the boundary-scan TCK signal in accordance with the impedance characteristics of each scan chain to minimize reflections. Teradyne offers combined ICT and boundary scan with its GR TestStation system and Scan Pathfinder software as well as with its Spectrum ICT system and Victory boundary-scan software.
Albee says Teradyne is now looking to combine the features of Scan Pathfinder, inherited with last year's acquisition of GenRad, with the features of Victory into a single package that will work with Teradyne's products that provide integrated schematic and board viewers, test-access analysis, and distributed test-strategy development. The company, says Albee, also plans to add a standard boundary-scan feature to its Pilot flying-probe tester. Currently, he says, the company will integrate the Pilot with third-party boundary-scan tools.
What the company doesn't plan to do, he says, is establish an exclusive relationship with one boundary-scan firm: "We believe it is valuable to establish a relationship with the independent boundary-scan tool providers, but unlike Agilent, we don't think it is in our best interest to work with only one vendor. Most of our customers are already working with their boundary-scan tool provider of choice in the engineering lab. They want to use the vectors they have already developed and do not want to be forced to buy and learn a different boundary-scan tool." Teradyne, he says, will work with any boundary-scan tool provider that a customer requests to integrate that firm's tools with its ICT systems.
Speaking from the boundary-scan side, Blasberg of Corelis agrees. An ICT vendor in an exclusive relationship with a boundary-scan-tool supplier will hurt itself as well as its customers if it tries to lock those customers into what may be a less-than-optimum boundary-scan solution for a particular customer application. Acculogic's Taheri says ICT vendors should pursue not a one-to-one but a one-to-many cooperative effort with boundary-scan firms, and vice versa. But tight integration is a key, all observers agree, and whether acceptable levels of integration require exclusive relationships remains debatable.
No one recommends wheeling up a boundary-scan controller next to an in-circuit tester and trying to simultaneously apply separately developed boundary-scan and in-circuit test programs. One reason is that such an approach would greatly complicate the test-development effort—you would face two development tasks instead of one. Furthermore, you'll have no way of knowing whether your two test programs provide full fault coverage or, alternatively, whether you're wasting valuable production-test time looking for the same faults with both test approaches.
Finally, notes Odbert, you could damage the board under test. Such damage could result from isolation problems between ICT and boundary-scan test-hardware power supplies or from the efforts of boundary-scan and ICT systems to simultaneously assert conflicting logic signal levels on one node. Woppman says that a coordinated approach eliminates that problem by driving unused nails to a high-impedance state during boundary-scan tests.
Despite the synergy that boundary scan and ICT can bring to test chores, the combination isn't perfect for every application. For low-volume production, Woppman says, a dedicated boundary-scan tester coupled with, perhaps, a flying prober to test resistors and other non-scan parts might be sufficient. Odbert concurs, saying that boundary-scan test plus a simple manufacturing-defects analyzer might be sufficient for high-volume, low-cost PCBs for consumer products, while ICT might remain most effective for a multi-thousand-dollar network card. "We don't know what the future holds," Woppman concludes, saying that successful test companies will offer flexible combinations of hardware and software from which you can choose.
|Vendors mentioned in this article|
Markham, ON, Canada
Santa Clara, CA
|Teradyne, Assembly Test Div.
Walnut Creek, CA