Home>Design & Prototyping Test Center>Test How-To

Getting 1000x test compression during wafer test

Ron Press, Mentor Graphics- July 20, 2012

Embedded test compression is a standard technique for dramatically reducing the test data volume and test time on the automatic test equipment. Companies typically aim for 60x to 100x compression for the device test. In the drive to further reduce test time, however, many companies test multiple die in parallel, referred to as multi-site testing. This is especially true for wafer test. It necessitates the use of as few pins as possible so that more devices can be tested in parallel. Users will optimize the packaged device test compression using the available pins to achieve the maximum compression with the maximum possible coverage. However, that same compression can be used with just one channel at wafer test letting you can crank compression up to 1000x, 2000x, or more. There is usually some minor loss of test coverage with the very high compression, which is fine because the goal is to serve as a coarse filter, weeding out most defective die prior to packaging. The more complete coverage can be done during test of the packaged device.

The strategy of using multi-site, low pin count testing (LPCT) on the wafer followed by full-coverage test on the packaged device is called dual-mode compression (Figure 1). It involves optimizing compression with the available packaged pins, and having a second level of test channel access to the compression logic with just a few pins. This way, a device might have 16 test channels for packaged device test and 100x compression, but the same compression could use only one channel during wafer test. You can get compression of 1000x or more, but with some small loss of test coverage. I have experience with several cases where companies use over 1000x compression and see 2% or less test coverage loss.

Figure 1. A general diagram of multi-site test. More parallel test is possible if the number of pins used during test is kept to a minimum.

The multi-site test part of the dual-mode compression depends on a technology called low pin count test (LPCT). LPCT places some of the static compression control signals and a state machine/counters to manage the scan_enable signal and pattern types inside the embedded test logic. As a result, as few as three test pins can be used to run the scan compression tests. A tester only needs to connect to clock, data_in and data_out. Some of the initial usage for LPCT compression was for devices with only a few pins available on the package, such as smart cards and imaging devices. However, LPCT is also now very useful for controlling the number of top-level routes in devices with many compression blocks and for multi-site test.
You can use a compression analyzer to quickly evaluate trade-offs between full dual-mode compression coverage for the packaged device and a very aggressive, 1000x range compression during multi-site LPCT wafer test. Figure 2 shows a dual-moe test setup. Some companies have been using this approach for years and test over 1000 devices in parallel using dual-mode compression and LPCT. I have even seen some companies take the opposite approach for dual-mode compression where more channels are used for wafer and packaged device test, but only one channel LPCT for a special in-system scan test feature. Whatever approach you choose, the use of a dual-mode compression strategy is proven to improve your test process.


Figure 2. Diagram of a dual-mode test setup. Config 1 would be used for the multi-site test for the wafer and uses few pins. Config 2 would be used for the packaged device and uses more pins for optimized compression with full coverage.

For an overview of test compression, LPCT, and multi-site testing, you can watch this video, helpfully titled Test Compression and Low Pin Count Test. http://go.mentor.com/29b94

Ron Press is the technical marketing manager of the Silicon Test Solutions products at Mentor Graphics. The 25-year veteran of the test and DFT (dseign-for-test) industry has presented seminars on DFT and test throughout the world. He has published dozens of papers in the field of test, is a member of the International Test Conference (ITC) Steering Committee, and is a Golden Core member of the IEEE Computer Society, and a Senior Member of IEEE. Press has patents on reduced-pin-count testing and glitch-free clock switching.