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Test method improves PWB reliability

Paul Reid, PWB Interconnect Solutions- August 2, 2012

Engineers have long used thermal-cycle testing determine the reliability of PWBs (printed wire boards). Traditionally, engineers have used thermal-cycling ovens, liquid to liquid and fluidized sand, and other methods to heat devices under test. Another method has been developed called Interconnect Stress Test (IST). The IST method is a thermal cycling type of reliability test for PWBs that is fast and flexible. IST can achieve 500 cycles in two days as compared to thermal cycling ovens which take three weeks for the same number of cycles.

The IST method uses representative coupons fabricated on the edge of PWB production panels. Special built-in heating circuits heat the coupons, which reduces cycle time when compared to heating with traditional thermal ovens. With ovens the environment heats the coupon. Coupons are subjected to thermal excursions associated with assembly and rework commonly called preconditioning. After preconditioning, each coupon is tested.

As coupons are exposed to thermal excursions, typically to 150°C in 3 min., small cracks occur in the copper interconnections, increasing the resistance of the test circuit. Testing is automated and stops within seconds of a circuit reaching a failure: a 10% increase in resistance. Because testing stops within seconds of reaching a 10% increase in resistance, the failing circuits don’t open. The failed circuits are are still conductive and may have a current applied while the coupon is observed using a thermal camera. Viewed with the thermal camera, a hot spot shows the most damaged interconnection. A microsection of the most damaged interconnection and the adjacent interconnections can then be processed and subjected to failure analysis.

The coupons also have capacitance circuits that correspond to the power planes within the PWB. Measurements on the capacitance before test, after preconditioning, and at the end of the test can reveal material degradation. A 4% drop in capacitance in an IST coupon reflects material degradation caused by delamination, cohesive failure, and crazing. Between these two techniques, IST finds reliability problems associated with copper break down and material damage caused by assembly and rework and anticipates field life.

The test coupon (Figure 1) is designed to replicate the board attributes. This includes the type of interconnections, layer count, copper weights, tightest grid size, smallest hole size that is in the PWB. The coupons all have a power circuit, used to heat the coupon, and a sense circuit. Both the power circuit and the sense circuit are monitored for changes in resistance during testing. All the attributes of the board are reflected in the coupon with the exception of line widths. The line widths are adjusted on layers 2 and 3 and N-1 and N-2 to allow the correct resistance on the power circuit in order to expedite coupon heating. The line widths are adjusted on the sense circuit, typically on layers 1/2 and N/N-1, to improve the sensitivity of the interconnections. The number of interconnections in the typical coupon is hundreds making the coupon sample size statistically significant to the board which has thousands of interconnections.

Figure 1.A typical Single-Sense Coupon has a structure of four terminals for connecting power and sense wires prior to testing.

The illustration shows the typical IST coupon design. Note the power and sense circuits are yellow and blue, respectively. The power circuit has current applied that heats the coupons while the sense circuit is passively heated. This means the power circuit is being tested under an electrical load while the sense circuit is tested passively. The power circuit tests the PWB’s outer layer’s internal interconnections while the sense circuit tests the whole interconnection. During testing, the resistances of both circuits are measured every 3 s.

Not only do IST coupons have power and sense circuits, they also have capacitance circuits. The capacitance circuits are known as DELAM circuits. The capacitance circuit is simply a large plane of copper. These circuits are typically on ground planes. So if there are ground planes on layer 3, 5, 7, 9, 11, 13 and 15 in the PWB, there will be DELAM circuits on those same layers.

Coupons are collected and sorted for testing. The resistance is measured and recorded for each circuit. In the power circuit, variations in resistance are a reflection of etching and registration. In the sense circuit, the resistance is a reflection of the copper volume, the copper thickness and distribution within interconnections. A high resistance in the sense circuit suggests low copper plating or poor copper distribution.  A low resistance suggests that the copper plating is thick and the distribution is uniform. The coupons are frequently sorted to include high, mid-range and low resistance coupons. Using this method the well plated, mid-range, and not so well plated coupons are subjected to testing.

Not only is the resistance measured but also the capacitance is measured and recorded (Figure 2). The capacitance measurements are recorded between each adjacent capacitance circuit. The capacitance of all circuits are plotted and a construction profile is created. If there is a change in construction, say a dielectric layer is missing; it will be obvious in the construction profile.


Figure 2. A Capacitance Construction Profile can reveal problems such as a missing dielectric.

The IST test method is to heat each coupon individually. The heating is internal on the traces between holes on the outer layers, (layers 2/3 and N-1/N-2) of the coupon. The heating cycle is to heat the coupon to the test temperature in 3 min. [±] 3 s There is no hold time at temperature, so as soon as a coupon reaches its test temperature, the heating stops. When the heating stops, the coupons are cooled by blowing air at ambient temperature. This method allows most coupons to cool to ambient temperature within two minutes. Testing is usually performed to 150°C for most interconnections. Microvias are tested at 190°C. Some materials like polyimide are tested at 210°C. Whatever the test temperature, the objective is to heat the coupon in three minutes ±3 s. Figure 3 shows a typical IST tester.


Figure 3. An IST tester can perform the measurements

After two cycles of testing, the coupons are subject to a simulation of assembly and rework--preconditioning. The assembly simulation is three thermal excursions to 230°C in the case of tin-lead assembly and 245°C or 260°C in the case of lead-free assembly. The preconditioning cycle is preformed just like the test cycle. We heat the coupon to its preconditioning temperature in three minutes ±3 s. The three cycles represent two passes down a reflow oven and a one-hand soldering cycle. Assembly and rework is performed with six thermal excursions to the reflow temperatures. Six thermal excursions represent the three thermal excursions of assembly plus a BGA remove and replacement and one touch up by hand. Figure 4 shows a coupon attached to the tester.


Figure 4. An IST tester connects to coupons on PWBs.

After the coupons undergo preconditioning three or six times to simulate assembly or assembly plus rework, we measure their capacitance again. A 4% drop in capacitance is indicative of material degradation and we select the coupon for microscopic evaluation. If we observe significant material damage, set stop IST testing. If there is no significant capacitance change, then testing continues.

Testing continues until there is a failure or the test ends. A failure is usually set at a 10% increase in resistance. Once the power or sense circuit reaches the 10% increase, testing stops within 3 s. A failure may occur anytime in the two cycles prior to preconditioning, during preconditioning, or during the rest of the test. If the coupons are robust, they will last until end of test which is typically 500 cycles. Using a typical IST cycle time of 5 min.--3 min. of heating followed by approximately 2 minutes of cooling to ambient--the test period is 2500 minutes or approximately 500 cycles over two days.

Typical causes of a failure are z-axis expansion during thermal heating of the copper interconnection, or material degradation. Note that the animation after Figure 5 shows a cross section on a PWB heated to 260°C. The PTH (plated through hole) and stacked structures act like rivets preventing the dielectric from expanding. The dielectric is constrained in the x and y axis by the warp and the weft of the fiberglass, but there is no internal constraint in the z -axis expansion. Figure 5 shows that the material squeezes out between the PTH and stacked microvias on the buried via that offers some degree of stress relief. The thermal expansion causes cracks in the copper which in turn causes an increase in resistance. Thermal excursion also degrades the epoxy of the dielectric system. These two degradations are seen as either a reduction in cycles to failure or material damage.


Figure 5. Thermal excursion occurs as a result of heating and cooling as the material squeezes. Cracks cause an increase in resistance. Play the animation below to see the results of heating and cooling.


Thermal excursion is caused by heating and cooling.

We perform data analysis on the cycle to failures of the group of coupons. The mean, standard deviation, minimum, maximum, range, and the coefficient of variation are all calculated. The coefficient of variation is the standard deviation divided by the mean expressed as a percentage. We record not only is the cycle-to-failure data recorded, but the percent change in resistance as well. The percent change in resistance is the amount of increase in resistance incurred by the circuit when the testing stopped. Thus if a circuit survived 500 cycles but had a 9% percent change at cycle 500, you know the circuit was just a few cycles from failing. Again the mean, standard deviation, minimum, maximum and range are calculated for each percent change but not the coefficient of variation.  

The example below is of compliance testing in which testing stops at the minimum requirement of 350 cycles. The coupon identification is in the first column of Table 1, labeled Coupon ID. The number of cycles the coupon achieved is in the power column. Power, the damage expressed as a percent on the power circuit, is in the next column labeled P %. The column Sense 1 is the number of cycles achieved by the sense circuit S1 and the percent of damage is in the next column labeled S1 %.


Table 1. Cycle to Failure Data

The Comb column is the lowest number of cycles from the Power or the Sense 1 column followed by the results column. In the Results column Accept indicates that the circuit passed the minimum requirement while an entry of P or S1 indicates which circuit failed. The calculation of mean, standard deviation, minimum and maximum cycles to failure are in the next five rows followed by the range. The last row is the coefficient of variation (standard deviation divided by the mean expressed as a percentage).

We enter N/A (not applicable) wherever the circuit didn’t fail but the other circuit failed before the end of the test. Note that coupon #13 didn’t fail, but was in the process of failing because it logged 6.6% damage accumulation at end of test. Coupon #17 failed on the S1 circuit after 254 cycles. Coupon #21 failed on the power circuit after 153 cycles. Green means that the circuits survived until end of test and the percent change on a circuit was less than 2%. The yellow highlight indicates that the circuits passed until the end of the test but the percent change was greater than 2%. The red means the circuit failed before the requirement of, in this case, 350 cycles. This lot failed the 350 minimum cycles to failure.

Another useful method of looking at the data is a damage accumulation graph (Figure 6). This is a graph of the resistances expressed at the peak temperature at each cycle during the test. Since the resistance is a reflection of the number of cracks in the circuit, it is a graph of how damage is accumulating during the test. For example, in the resistance graph illustration, plot “A” would be considered a catastrophic failure. “B” shows damage from preconditioning. “C” and “D” show accelerated damage after onset. “E” shows that the damage profile was affected by delamination. “F” and “G” reflect robust coupons while “F” is most likely failing due to a wear out type of failure, metal fatigue.


Figure 6. A resistance graph indicates how damage accumulates during a test.