Eye Diagram Basics: Reading and applying eye diagrams
Deepak Behera, Sumit Varshney, Sunaina Srivastava, and Swapnil Tiwari, Freescale Semiconductor- December 16, 2011Accelerating data rates, greater design complexity, standards requirements, and shorter cycle times put greater demand on design engineers to debug complex signal integrity issues as early as possible. Because today's serial data links operate at gigahertz transmission frequencies, a host of variables can affect the integrity of signals, including transmission-line effects, impedance mismatches, signal routing, termination schemes, and grounding schemes. By using an oscilloscope to create an eye diagram, engineers can quickly evaluate system performance and gain insight into the nature of channel imperfections that can lead to errors when a receiver tries to interpret the value of a bit.
A serial digital signal can suffer impairments as it travels from a transmitter to a receiver. The transmitter, PCB traces, connectors, and cables will introduce interference that will degrade a signal both in its amplitude and timing. A signal can also suffer impairments from internal sources. For example, when signals on adjacent pairs of PCB traces or IC pins toggle, crosstalk among those signals can interfere with other signals. Thus, you need to determine at what point to place the oscilloscope probe in order to generate an eye diagram that will help you locate the source of the problem. Furthermore, where you place an oscilloscope's probe will produce differing signals on the display.
Generating an eye diagram
An eye diagram is a common indicator of the quality of signals in high-speed digital transmissions. An oscilloscope generates an eye diagram by overlaying sweeps of different segments of a long data stream driven by a master clock. The triggering edge may be positive or negative, but the displayed pulse that appears after a delay period may go either way; there is no way of knowing beforehand the value of an arbitrary bit. Therefore, when many such transitions have been overlaid, positive and negative pulses are superimposed on each other. Overlaying many bits produces an eye diagram, so called because the resulting image looks like the opening of an eye.
In an ideal world, eye diagrams would look like rectangular boxes. In reality, communications are imperfect, so the transitions do not line perfectly on top of each other, and an eye-shaped pattern results. On an oscilloscope, the shape of an eye diagram will depend upon various types of triggering signals, such as clock triggers, divided clock triggers, and pattern triggers. Differences in timing and amplitude from bit to bit cause the eye opening to shrink.
Interpreting an eye diagram
A properly constructed eye should contain every possible bit sequence from simple alternate 1’s and 0’s to isolated 1’s after long runs of 0’s, and all other patterns that may show up weaknesses in the design. Eye diagrams usually include voltage and time samples of the data acquired at some sample rate below the data rate. In Figure 1, the bit sequences 011, 001, 100, and 110 are superimposed over one another to obtain the final eye diagram.
A perfect eye diagram contains an immense amount of parametric information about a signal, like the effects deriving from physics, irrespective of how infrequently these effects occur. If a logic 1 is so distorted that the receiver at the far end can misjudge it for logic 0, you will easily discern this from an eye diagram. What you will not be able to detect, however, are logic or protocol problems, such as when a system is supposed to transmit a logic 0 but sends a logic 1, or when the logic is in conflict with a protocol.
What is jitter?
Although in theory eye diagrams should look like rectangular boxes, the finite rise and fall times of signals and oscilloscopes cause eye diagrams to actually look more like the image in Figure 2a. When high-speed digital signals are transmitted, the impairments introduced at various stages lead to timing errors. One such timing error is “jitter,” which results from the misalignment of rise and fall times (Figure 2b).
Jitter occurs when a riding or falling edges occur at times that differ from the ideal time. Some edges occur early, some occur late. In a digital circuit, all signals are transmitted in reference to clock signals. The deviation of the digital signals as a result of reflections, intersymbol interference, crosstalk, PVT (process-voltage-temperature) variations, and other factors amounts to jitter. Some jitter is simply random.
In Figure 2c, the absolute timing error or jitter margin is less than that in Figure 2b, but the eye opening in Figure 2c is smaller because of the higher bit rate. With the increase in bit rate, the absolute time error represents an increasing portion of the cycle, thus reducing the size of the eye opening. This may increase the potential for data errors.
The effect of termination is clearly visible in the eye diagrams generated. With improper termination, the eye looks constrained or stressed (Figure 3a), and with improved termination schemes, the eye becomes more relaxed (Figure 3b). A poorly terminated signal line suffers from multiple reflections. The reflected waves are of significant amplitude, which may severely constrict the eye. Typically, this is the worst-case operating condition for the receiver, and if the receiver can operate error-free in the presence of such interference, then it meets specifications.
As can be seen in Figure 4, an eye diagram can reveal important information. It can indicate the best point for sampling, divulge the SNR (signal-to-noise ratio) at the sampling point, and indicate the amount of jitter and distortion. Additionally, it can show the time variation at zero crossing, which is a measure of jitter.
Eye diagrams provide instant visual data that engineers can use to check the signal integrity of a design and uncover problems early in the design process. Used in conjunction with other measurements such as bit-error rate, an eye diagram can help a designer predict performance and identify possible sources of problems.
FOR MORE INFORMATION
“High Frequency Electronics,” www.highfrequencyelectronics.com.
“Anatomy of an Eye Diagram,” Application note, Tektronix, September 2010. www2.tek.com/cmswpt/tidetails.lotr?ct=TI&cs=apn&ci=17668&lc=EN
Deepak Behera is a design engineer with experience in signal integrity.
Sumit Varshney is a senior design engineer with expertise in physical integration, package designing and signal integrity.
Sunaina Srivastava is a senior design engineer with experience in embedded systems, board designing, and signal integrity.
Swapnil Tiwari is a design engineer with experience in microwave antenna designing and signal integrity.