How to test high-speed memory with non-intrusive embedded instruments, Part 1
Alfred Crouch- September 4, 2012The problem with memory test
Recent surveys of working engineers in the electronics industry by the International Electronics Manufacturing Initiative (iNEMI) found that testing memory and memory buses on circuit boards is one of the most pressing problems for designers and manufacturers (www.inemi.org). Many factors have contributed to this problem.
First, there is the disappearance of test pads on circuit boards to enable design debug with oscilloscopes and logic analyzers in design, and, in manufacturing, bed-of-nail fixtures for in-circuit test (ICT), manufacturing defect analyzers and flying probe systems. Second, there are the restrictions on placing any sort of a test probe on high-speed memory buses because of the capacitive signal distortion created by the probe. Third, memory bus protocols are becoming increasingly complex. And, finally, there are a host of other factors, including manufacturing process variations.
Fortunately, a number of non-intrusive board test (NBT) or probe-less methods for testing memory, including boundary-scan test (BST), functional test, processor-based testing methodologies such as processor-controlled test (PCT), FPGA-based testing mechanisms such as FPGA-controlled test (FCT) and embedded memory built-in self-test (memory BIST) can be deployed without relying on probes or test pads on circuit boards. Each method has its advantages and disadvantages. Implementing any one method will involve tradeoffs. Deploying several can deliver the debug and test coverage no longer possible with legacy methods. This three-part series of articles will describe these various non-intrusive debug and test methods and explain some of the most salient tradeoffs. In particular, some of the complexities involved with testing the high-speed DDR (double data rate) memory bus will be explained.
What’s the problem?
One of those iNEMI surveys asked engineers what their biggest problems were with testing circuit boards. Of the 11 possible problems listed, characterizing and testing memory soldered to circuit boards was among the top three. Also at the top of the list was ‘loss of access to test points’ and ‘the need to perform debug/diagnostics on board failures.’ When asked which type of built-in self-test (BIST) instruments would solve the engineer’s problems best, memory BIST was rated the second most needed, virtually tied with BIST instruments for validating high-speed I/O buses. Clearly, the ability to thoroughly test, characterize and diagnose problems with soldered-down memory is one of the most pressing problems in the industry.
In most cases, board designers who are doing board debug as well as manufacturing test engineers assume that the memory devices themselves are not causing a failure since the chips are tested and qualified before they are assembled on a board. As a result, a memory test failure should indicate a failure in the connectivity channel to the memory. Previously, when memory speeds were not as high as they are today and communications protocols over memory buses not so complex, performing static shorts-and-opens testing on memory interconnects might suffice. Now though, signal propagation through passive devices such as capacitors and the signal integrity on high-speed traces to memory must be validated and characterized for an open data window. Often, this data window will demonstrate sensitivities to clock jitter, temperature, electrical noise as well as the level and stability of the voltage.
One of the several factors that have exacerbated the difficulties test engineers have with memory is the complexities of these buses. Many of the most prominent memory buses, such as the various generations of double-data-rate (DDR) memory, have achieved very high data transfer rates at the expense of simplicity. Indeed, each generation’s higher data rates have only exacerbated the difficulties of testing memory buses. A closer look at the complexities of the basic architecture of the DDR memory bus illustrates this point.
Data transfers to DDR memory are able to achieve their high speeds, DDR1 was rated up to 400 mega-transfers per second (MT/s), DDR2 up to 1066 MT/s and, DDR3 up to 2133 MT/s, because both the rising and falling edges of a signal (Figure 1) communicate a bit of data and the IO clock can be four times faster than the internal memory clock.
Figure 1: DDR signals carry data on rising and falling signal edges
Slower, previous generation bus architectures could transfer only one bit on either the rising or falling edge of a signal. DDR is able to communicate a bit on both the rising and falling edges because it is a source-synchronous memory bus whereby the clock that is required to synchronize the DDR signals at the receiver is communicated over the DDR bus along with data and address signals. The clock, which is sometimes referred to as a strobe, is usually generated by the same device that generates the data and address signals, such as a memory controller, because this device’s process-voltage-temperature (PVT) variation is likely to be more consistent than it would be if the clock were generated by another device.
When the clock is properly synchronized with the data and address signals, both the rising and falling edges of the clock signal will be correctly synchronized at the receiver and two bits of data will be transmitted during one cycle of the DDR clock without synchronizing any phase lock loops (PLL) or using any clock/data recovery schemes. At this level of complexity, structural shorts and opens are not the only causes of failed memory transfers. The integrity of the clock, data, and address signals may be susceptible to temperature, jitter, noise, voltage aberrations and other environmental conditions. In addition, these high-speed memory signals are very sensitive to board manufacturing variations in resistance, capacitance, inductance and others. Any of these factors can adversely affect the timing of the data window that is needed for a valid DDR memory transfer.
Often the DDR bus must be tuned by adjusting the parameters of the data window to optimize data throughput. Failing to achieve a valid data window on a particular circuit board’s DDR bus may indicate that the manufacturing process which produced the board exceeds design tolerances or is defect prone.
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