PCI Express update: the next, next, next generation
Ransom Stephens- July 25, 2012Gen four is coming! Hide.
Al Yanes, President of the PCI-SIG (Peripheral Component Interconnect &endash; Special Interest Group), held a party in Santa Clara last week to celebrate “Twenty years of PCI technology and twenty years of innovation.”
Ramin Neshati, the PCI-Express Serial Communciations Working Group Chair, said “All future client-based storage attachments will use PCI-Express.”
Yanes and Neshati introduced plans for PCIe 4.0. Here's a summary of the generations:
• PCIe 1.0: 2.5 GT/s = 2.0 Gb/s with 20% overhead from 8b/10b encoding.
• PCIe 2.0: 5 GT/s = 4.0 Gb/s with 20% overhead from 8b/10b encoding.
• PCIe 3.0: 8 GT/s = 7.88 Gb/s with 1.5% overhead from 128b/130b encoding.
And new PCIe 4.0: 16 GT/s = 15.76 Gb/s with1.5% overhead from 128b/130b encoding.
Every generation supports multiple signaling widths, scaling the available data rate by introducing more lanes: ×1, ×4, ×8, ×16.
Backward compatible to PCIe 1.0, PCIe 4.0 will follow the same essential rules as previous generations, supporting up to 32 serial lanes in one connector. The upgrade from the first generation, which has 2.0 Gb/s at 2.5 GT/s, will support ever thinner devices. One lane of PCIe 4.0 will support the data rate of the ×8 version of PCIe 1.0. And fully loaded at ×16, PCIe 4.0 will be able to haul a tidy 256 GT/s.
The PCIe 4.0 specification will support cable lengths of 1-2 m and 8-10 in on standard FR-4 PCB (flame retardant type 4 printed circuit board (i.e., the same stuff you've been using all your life)). Users are welcome to extend the reach at their own risk (and reward) and they are considering including a standard for repeater technology to ease extensions.
Neshati said that the bandwidth improvement from 3.0 to 4.0 will be attained through improved silicon and channel improvements like routing geometry. They will "reoup lost margin in the connector." The new connector will be mechanically identical to PCIe 3.0, but electrically improved and backward compatible to PCIe 1.0.
Neshati added that he expects "PCIe 4.0 to be more of an implementation challenge than a specification challenge" by virtue of the unique tack that the PCIe standards committee took in developing PCIe 3.0. Rather than prescribe interoperability standards based on acceptable worst cases, they embraced statistical analysis so that the standard could address only those edge cases with a reasonable likelihood of causing BER (bit error ratios) to exceed the prescribed minimum.
Referencing the rule of thumb that roughly five years passes from initiating a specification to delivery, Yanes said, "Expect the PCIe 4.0 specification to be released in late 2014 and to impact designs in 2017."