IJTAG standard streamlines chip validation

Test & Measurement World Staff- September 11, 2012

A tutorial from Asset InterTech explains how the new IEEE P1687 IJTAG (Internal JTAG) standard simplifies and automates the way chip designers manage embedded instruments that perform chip validation and characterization. The IJTAG standard, which is expected to be voted on later this year, specifies a standard interface to instruments embedded in chips and defines a methodology for accessing them, automating their operations, and analyzing their outputs.

Asset’s IJTAG tutorial describes the on-chip IJTAG architecture, as well as the two languages defined by the standard: ICL (Instrument Connectivity Language) and PDL (Procedural Description Language). ICL defines the connections among embedded on-chip instruments, and PDL is an extension of the popular Tcl (Tool Command Language) for developing validation, test, and debug vectors for execution by IJTAG instruments.

The IJTAG tutorial can be downloaded at www.asset-intertech.com/Products/IJTAG-Test/IJTAG-Test-Software/IJTAG-Tutorial.

Asset InterTech, www.asset-intertech.com