Signal integrity at DesignCon
Janine Love- January 7, 2013DesignCon is fast approaching, and will be taking place January 28-31st in Santa Clara, CA. I’ve been spending quite a bit of time lately thinking about signal integrity, so I am trying to pack my schedule with events covering that topic. If you are too, here is a list that can help you get started.
• Monday January 28th 130-430 Ballroom E Tutorial: Design and Verification for High-Speed I/Os at Multiple to >40 Gbps With Jitter, Signal Integrity, and Power Optimization
• Monday, January 28 4:45 PM–6:00 PM - (Location: Ballroom E): Case of the Closed Eye: A Growing 100G Dilemma (Panel)
• Tuesday, Jan 29th: 1105-1145 Ballroom H: High-Throughput, High-Sensitivity Measurement of Power Supply-Induced Bounded, Uncorrelated Jitter in Time, Frequency, and Statistical Domains
• Wednesday January 30th: 250-330 Ballroom F Understanding Apparent Increasing Random Jitter with Increasing PRBS Test Pattern Lengths
I’m open to more suggestions, so if you know of a paper, panel, or product I should see, sound off in the comments!