DesignCon Report: Making things happen

Janine Love- January 30, 2013

After narrowly escaping the snow falling in NJ Monday morning, I made my way to DesignCon 2013 in Santa Clara in time to catch a longstanding panel: The Case of the Closed Eye starring T&M World’s own Ransom Stephens as well as Chris Loberg from Tektronix, Erick Kvamme from LSI Corp., Mike Li from Altera Corp., Greg LeCheminant from Agilent, Marty Miller from LeCroy, and Pavel Zviny from Tektronix. The bottom line from this panel is that higher data rates require better test and measurement equipment and better, more intelligent test patterns. 

During the panel, Marty Miller specifically asked the question, “Is the time testing using long data patterns spent wisely?” in response to Erick’s report on how long it took him to acquire the data that underscored most of the analysis by the panel. And, Greg LeCheminant considered the questions, “what is clock recovery doing to my jitter measurements?” and “how does PLL behavior impact measurement?” He warned that it is important for test equipment manufacturers to be careful of how they do clock recovery, because long patterns, such as PRBS31, stress a test instrument’s clock recovery capability.

Tuesday morning, I attended a paper session, “Channel to Channel Crosstalk Behavior and Design Optimization for DDR4 Signaling,” which is a DesignCon Paper Award Finalist. The paper is by Xiang Li and James McCall of Intel. Unfortuantely, neither was able to attend, so James Casanova, also of Intel, gamely took over the presentation. In this work, the authors took used a motherboard with a CPU, riser card, and DIMMs to study the interfaces between the DDR4 channel and the memory buffer and the DIMMs and the memory buffer. The area of interest was underneath the memory buffer, where the connectors were, because that’s where they looked for crosstalk. The DDR4 channel had a coupling impact on the memory buffer channel, while the memory buffer had coupling impact on the DDR4 channel. The work included creating a 3D model that represents the memory buffer interface and the DDR4 connector. It included the stripline trace from the memory buffer channel and connector via from the DDR4 backside channel. A major takeaway from this analysis was to keep to single trace routing if possible.

In the morning, I managed to carve out a corner in Rohde & Schwarz’s standing room only “Phase Noise and Jitter Measurements” presentation by Rick Daniel. Rick did an excellent job explaining how phase noise measurements are made, and how one must consider the noise contribution of the test instrument when analyzing phase noise and jitter data. I’m going to ask Rick to write us an article on this for Test & Measurement World.

Later on Tuesday, I was able to see a demonstration of Agilent’s Physical Layer Test System (PLTS) 2013, which  provides signal integrity analysis of high-speed interconnects (including cables, connectors, PCBs, and backplanes). This product emphasizes the growing importance of performing analysis and characterization of interconnects, because even the smallest physical geometries in a system can effect a high-speed measurement.

After my visit with Agilent, I managed to catch Patrick Mannion, Brand Director for EDN, T&M World, and Planet Analog, hand out the DesignVision Awards http://www.edn.com/design/systems-design/4405951/he-2013-DesignVision-winners-announced-at-DesignCon, where Teledyne LeCroy won in the test and measurement category for its HDO High Definition Oscilloscope.

Soon after, I stopped by Teledyne LeCroy’s booth and talked with Alan Blankman, Technical Product Marketing Manger for Signal Integrity, who gave me a great demo of the company’s SPARQ signal integrity network analyzer, which features “hands off calibration” with built-in calibration standards in an effort to make it much simpler for designers to analyze cross talk. He also gave me a demo of the companies SDA3 Complete Link serial data analysis package (see video) which supports multi-lane serial data up to four lanes to measure eye, jitter, vertical noise, and to quantify crosstalk. You can use this package to either capture four lanes or prove in four places at a time on a circuit. This product also offers “virtual probing” for when you cannot get a probe under a chip. While at the LeCroy booth, also grabbed a quick demo on their PCIe protocol analysis products.

Next stop… NI, Tektronix, and the Best in Test Awards…