Mentor Graphics announces partnership with NXP for DFT
Test Measurement World Staff- May 6, 2008
Mentor Graphics has announced a partnership with NXP Semiconductors in which NXP will use Mentor’s design-for-test (DFT) products, including the TestKompress compressed-pattern-generation and YieldAssist failure-diagnosis tools, to improve the quality and time-to-market of NXP’s products. The agreement also provides interim support for NXP’s test tools.
See " Mentor Graphics acquires NXP design-for-test technology, developers ," in which Greg Aldrich, director of marketing for Mentor's DFT product line, comments on NXP's DFT technology and team.
“NXP believes that a partnership with Mentor Graphics is the most effective way to continue to meet our manufacturing test needs and to deliver the highest quality devices to our customers.” said René Penning de Vries, senior VP and CTO, NXP Semiconductors. “’First-time-right’ being a crucial element of the manufacturing and design process, NXP selected Mentor’s technology for testing before tape-out and silicon to help improve our time-to-market…. Our partnership allows NXP to use commercial DFT tools without disrupting any of our critical design projects.”
Under the agreement, Mentor Graphics also obtains rights to NXP’s internally-developed test tools, technology, and talent as a portion of NXP’s DFT tools development organization joins Mentor’s design-for-test product division. This division of Mentor is also establishing a new R&D facility in Hamburg.
“We’re excited about our new business relationship with NXP. It not only brings new DFT technology to Mentor, but also brings the talent of world-class DFT developers which will help us accelerate the development and delivery of innovative DFT technologies into the marketplace,” said Joe Sawicki, VP and GM of the design-to-silicon division at Mentor Graphics. “We expect the partnership to produce dividends for both parties and ultimately to create value that can be passed on to all Mentor DFT customers.”