Look Ahead to the Next Decade of Board Test
Bernard Sutton, GenRad Europe- October 1, 1999
As you encounter the challenges of reduced bed-of-nails access due to the introduction of new high-density component technologies in products, your production test strategy must change to ensure that you can continue to meet cost and quality targets. Industry predictions for semiconductor technology over the next decade seal the fate of in-circuit test (ICT) as a long-term viable test method. Just as the growth of ICs in the 1980s forced engineers and managers then to change their test strategy thinking and embrace ICT (see “ICT Supplants Early Functional Test” below), today’s IC technology predictions call for yet more new thinking in the way you will test boards over the next decade.
The main prediction is for ICT to see a steady test industry decline and leave a new and very much enhanced form of functional tester to carry board test forward through the next decade. The expected reduction in ICT, the increase in functional test platforms, and changes with their associated drivers are difficult to accurately predict but Figure 1 depicts a range of probabilities.
The shift at board test towards increased dependence on functional test for higher fault coverage will require the adoption of cost-effective generic functional test platforms that arrive ready compliant with production test features. These platforms and their supporting software tools must be designed to ensure that you can make the most efficient use of your test engineering resources.
As ICT steadily gives way to enhanced functional test, other process defect detection methods such as automatic optical inspection, flying probe, and X-ray will help bridge the gap, as will improved process control tools. But all these methods have some limitations of test capability or speed when compared with ICT. And, these methods normally still require some form of functional test to confirm product functionality.
As circuit complexity increases and silicon becomes dedicated to on-board and on-system built-in self-test (BIST), these technologies (along with others such as self diagnosis and auto repair) could become the dominant test methods of the far future. But it is unlikely that BIST will be capable of replacing process test and product verification test until new BIST design tools become available that have near zero impact on the product design cycle.
Analyse Industry Trends
If you analyse the trends within electronics design and component manufacturing, you will see some indicators of imminent and significant changes. These changes will set some tough challenges for those responsible for production test. Take, for example, the technology predictions in the 1998 road-map produced by the North American Electronics Manufacturing Initiative (NEMI).
NEMI ( www.nemi.org) is a partnership between commercial and consumer electronics manufacturers, semiconductor manufacturers, substrate suppliers, materials suppliers, equipment manufacturers, and electronics service providers. NEMI affiliates include electronics industry associations, government agencies, and research universities.
Extracts from NEMI’s road-map (see Table 1) link changing component technologies with expected changes in test over a ten-year period. The main point you see is that relatively rapid adoption of higher density I/O component packaging styles will force a reduction in access and space for dedicated test pads.
Another semiconductor road-map, from the National Technology Road-Map for Semiconductors in 1997 (see Table 2), predicts that we’ll see component pin counts of up to 2690 by the year 2012. For this to happen, the industry will need to address several factors. The most fundamental factor is size.
Size Creates Big Problem
Size, and the heat generated within a package, present huge problems of electrical connection due to thermal expansion and contraction. As silicon gate counts have increased, the die size has naturally increased to accommodate the additional gates. Continued developments in silicon manufacturing techniques are maintaining the trend to integrate more gates per cm2 but the die size is still set to increase. The higher functionality has, at the same time, increased the I/O pin-count requirement. The answer until recently was to have larger and larger component packages to accommodate the high pin-count and thermal expansion issues. Pin grid array (PGA), quad flat pack (QFP), ball grid array (BGA), and micro ball grid array (mBGA) are all attempts to increase pin count in smaller component footprints. Manufacturers have largely integrated these packages into surface mount technology (SMT) assembly and test processes by upgrading existing machines. This upgrading cannot continue for ICT because the newer package styles will have counts of several hundred pins per cm2. This pin density will not allow for bed-of-nails test pin access or the addition of dedicated test pads. Whilst the adoption of the newer package styles will not happen overnight, and even then not necessarily across the electronics industry, you should now be preparing the test strategies that meet your customers’ future expectations of product cost and quality.
Until BIST and self-repair technologies become mainstream, you need to consider how to achieve the twin objectives of high product quality and reduced cost of test as your traditional end-of-line process tests become less effective. The objective of reducing cost will have an increasingly larger influence on test strategies as you move forward. Traditional ICT/MDA test systems will continue to provide a very cost-effective method of removing process defects where full or partial bed-of-nails access prevails. These systems can provide test times matched to line beat rates. They can also be run by production operators or, increasingly, be automated. ICT programs for new and modified products are relatively simple to produce using tool sets that the equipment vendor provides. A single ICT system is usually capable of testing all product types. The system provides the operational environment, user interface, runtime software, security access, diagnostics, and the requirements for data interchange. Today, you still typically follow ICT by a functional test stage. This stage attempts to verify product functionality and remove the relatively few defects not detectable with ICT.
If you want to continue to reduce the cost of test, you can consider either combining test stages or distributing test fault coverage over the assembly line. Distributing test coverage — a long-standing attractive goal — gives potential large gains in product quality by early detection and correction of process defects at each manufacturing stage. But, where these gains require the insertion of additional test processes, the gains can be outweighed by the cost of test programs, labour, and possibly test fixturing.
Apply a Single Functional Test
Recognising that most products will still require some form of functional test before shipment to customers, a more logical approach appears to be to enhance the functional test stage and eliminate the need for ICT. Indeed, when you have little or no bed-of-nails access the only viable solution will be a single functional test stage.
The problem with adopting this approach to date has been in its implementation. Because of the traditionally high price tags associated with generic functional test platforms, “rack and stack” or “hot mock-up” functional test developments have appeared to be lower cost. These “point solutions” usually test only a limited range of products, and are often a subset of design verification tests inherited from design departments. These solutions, however, do have the advantage of being available at the time you introduce a product to manufacturing.
But, at that point, lower volumes and higher engineering focus mask problems to come. These problems usually surface when production volumes increase and deliveries must be met.
The first problem to appear is usually low throughput, which results from long test times, poor test reliability, and the unplanned repeat testing of failed units.
The second problem is low fault coverage, which appears when larger than expected numbers fail at the next stage of test.
The third problem, and usually the most costly to fix, results from poor product diagnostics. As a real example, a Unix system test in use as a high-end server by major clients, such as government departments, at one stage simply reported “Failed; Bad Magic” at the end of a 20-minute functional test run. That message was the only clue given to diagnostic engineers. This message was eventually traced to a software engineer who arranged that, at the start of BIST, the test loaded a register with a fixed number (his “magic” number). The number was re-examined at the end of test and his logical output message on a mismatch was the indeterminate “Failed; Bad Magic”.
Future Functional Features
The solution to all these problems requires future functional test platforms with many of the advantageous features we expect of today’s ICT systems. In particular, these features will allow you to program tests to address the actual defect fault spectrum.
Your checklist for this new breed of functional test system should include:
In addition, you may also wish to add the following features that allow global operations to replicate or transfer production at many differing sites:
You should already be enjoying all of the above features from your ICT systems provider. But, you’ll seldom find these features with “rack-and-stack” solutions and never with “hot mock-ups”.
OEM manufacturers have, for years, been able to successfully solve the problems of product verification testing by developing in-house functional test solutions. Whilst these solutions require low capital investment, they do require large amounts of test engineering time to design and support the bespoken solution for each new product. The solutions also often fall short of the requirements of production managers for integration into manufacturing shop floors. This situation has occurred even when the resultant verification tests were not required to also address defects previously detectable at earlier ICT/MDA test. The demands on the same engineering skills are set to increase as they now work to enhance the fault coverage of functional test solutions for products using the newer component packaging technologies.
Bernard Sutton is European manufacturing technologist with GenRad Europe, based in Stockport, UK. Bernard has 20 years’ industry experience of electronics manufacture and test, and has held senior positions in test engineering with companies such as TSL, D2D and British Aerospace.
For Further Reading
Herrel, Dennis, “Power to the Package”, IEEE Spectrum, July 1999.
“The 1997 National Technology Road-Map for Semiconductors”, www.sematech.org.public.home
“Board Assembly Process Technology Road-Map”, 1998 National Electronics Manufacturing Technology Road-Maps.
ICT Supplants Early Functional Test
In the early 1980s, complex boards were through-hole plated and included several hundred components, some of which may have been silicon parts in large dual-in-line packages. These parts were typically glue logic in packages with less than 50 pins. At that time you could still model fault conditions and implement functional tests in order to detect, and occasionally isolate, production as well as component defects. However, the high cost of developing and debugging these tests meant that only a few critical applications, such as military programmes, could afford this process. The time to develop these test packages was measured in parts of man-years, and often involved several test engineers working around the clock. Most of the development time was taken to provide fault isolation routines, because fault diagnosis was becoming increasingly difficult on mixed analogue and digital boards.
For functional test system vendors, the future then looked rosy because the growth in IC usage was set to increase the demand for test. At its peak, functional test systems cost $1 million plus and even included special power feeds and air conditioning to remove excess heat. What went wrong for these functional test vendors was that someone, and it’s not clear who, invented bed-of-nails in-circuit test (ICT).
Initially, designers were slow to accept ICT because of the requirement to provide test pads and design circuits capable of being “back driven”. (Back driving is an essential element of digital ICT, allowing the component’s normal logic state to be momentarily overdriven to the desired test state.) Back driving was largely an unproved technique and became the subject of many investigations and reliability reports. In fact, quality managers only accepted the technique when ICT vendors added programmable back-drive limits to their systems. Production managers were more receptive, though, because they needed a new test method to counter the exponential growth in functional test development times.
Commercially, ICT remains a resounding success where bed-of-nails access prevails. The test method strengths are its rapid cost-effective detection and diagnosis of process and component defects.