Go inside a PXI source-measure unit
Rolando Ortega, National Instruments- July 2, 2012Designing a high-performance instrument in the 3U PXI form factor takes a new mindset when compared to designing a traditional box instrument. Modular instruments, because of their small size, have no room for anything superfluous and anything inefficient is cut out. That forces designers to continuously look at new ways of doing things. When designing the latest PXI SMU (source-measure unit), we at National Instruments had to look at new parts, new strategies, and new architectures, riding the wave of Moore's law to take advantage of improvements in technology. Restrictions such as these often give rise to innovation.
Different SMU architecture
Figure 1 shows a high-level view of a traditional SMU archtecture. Some sort of digital device, typically an FPGA (field-programmable gate array) or microcontroller, uses a series of precision DACs to configure voltage-and-current setpoints on an analog controller to match the user's requirements. A power stage amplifies the controller's output and connects to the output through a current-sensing shunt resistor. The voltage across the shunt and the voltage at the output terminals feed back to the controller to close the control loop. We need closed-loop control to guarantee that the DUT (device under test) sees the exact value we configured despite its own electrical characteristics and the drop across the shunt. That constitutes the "Source" part of "SMU".
Figure 1. A traditional SMU architecture uses a microcontroller or FPGA to synthesize the digital representation of the SMU's analog output. Click on image to enlarge
The "Measure" part uses a path parallel to the controller feedback, where the voltage and current values are fed to precision ADCs to report actual behavior back to the user. Note the pink blocks in Figure 1. These are precision parts that need a considerable amount of filtering. They consume space, and power, and the add cost to the design.
This decades-old design duplicates certain efforts. If we're already measuring the current and voltage using ADCs connected to the FPGA, why can't we just run the control loop inside the FPGA? Figure 2 shows a high level view of what such an SMU would look like. Here, the controller has moved inside the FPGA, putting it in the digital domain. There's only one DAC now, and it's no longer a precision part because it's inside the loop. In the traditional design, a series of DACs provide voltage and current setpoints to the loop. The loop's output accuracy depends on how well the DACs perform. Once the control loop is run inside the FPGA, the set point is a digital value that will be compared against the ADC measurement. We still use one DAC to provide an analog signal to the power stage, but the accuracy of the output will be determined solely by the ADCs. Thus, the DAC doesn't need to be a precision part any more, and it doesn't need heavy filtering and conditioning. Now the ADCs play both the parts of feedback and measurement paths.
Figure 2. A digitally-controlled SMU uses an FPGA-based controller with two DACs and an ADC that monitors the system's output. Click on image to enlarge
Figure 3 shows the NI PXIe-4141 four-channel precision SMU. We chose PXI Express over PXI because it provides more power per slot and it uses our most recent interface ASICs. A PCIe x1 link connects to the STC3 (callout 1), an NI ASIC that serves as a PCIe PHY (physical layer) and includes a high-speed interface designed for isolated applications such as this one. The STC3 also provides a way to configure the FPGA on the board, allowing for field upgradeability. We use the Silicon Labs Si846x series of digital isolators (2) to provide high-speed communications and triggering to the FPGA (3). By isolating the FPGA along with the analog front end, we can directly control the switches, ADCs, and DACs of all four channels, as well as run all four digital control loops in the same part, effectively minimizing the board area. We chose the XC6SLX75 Spartan-6 FPGA from Xilinx because it provides abundant DSP slices, which are critical for this control-loop application.
Figure 3. This photo of a PXIe-4141 SMU shows how the analog and digital sections are kept separate, with analog circuits closer to the I/O ports. Click on image to enlarge
We use two AD5452 12-bit DACs (4) per channel in an overlapping configuration. In this way, we get the equivalent of a 20-bit DAC that can update within 200 ns. The non-linearity of the resulting composite DAC is not an issue because the DAC is within the control loop, and the high-precision ADC will determine the accuracy of the output. The output of the DACs is amplified using a THS6132 (5) from Texas Instruments. This dual ADSL driver is an ideal power stage for this application because of its class-G architecture. Two adjacent channels share one driver.
To measure current, we use a series of precision shunt resistors (7). The different current ranges and sense modes are controlled by a series of switches and analog muxes (6). The measurement is handled by two sigma-delta ADCs (8), built from discrete op-amps, resistor networks, and off-the-shelf SAR (successive-approximation register) ADCs to achieve the conflicting requirements of high-speed sampling and long-term precision and stability.
Digital Control Loops
Though it's easy enough to draw a diagram in which SMU components just dissolve into "digital processing," the actual implementation isn't quite so simple. In terms of physical requirements, the loop's main limitation is its turnaround time. SMUs operate on loop bandwidths in the 10s or low 100s of kilohertz. Thus, we need a control loop capable of handling sample, process, and output in under 2 Âµs. Here, advances in off-the-shelf ADCs and DACs, as well as the vast processing resources in FPGAs make the task at least theoretically possible.
Besides picking the right components, we also need software tools to increase our productivity to the point where a design such as this is not only possible, but also practical. In this case, we used one of our own tools, NI LabVIEW FPGA software, to quickly prototype and prove this new architecture. I am well versed in HDLs and hardware design, but the mere prospect of writing, verifying, debugging, and optimizing a closed-loop power controller using VHDL was a daunting proposition. LabVIEW FPGA gave me the right level of abstraction to deal with this particular problem. A simplified version of my control loop design is shown in Figure 4.
Figure 4. The controller block diagram, written in LabVIEW, includes digital filter, error-signal block, and integrator that drive's the SMU's DAC output. Click on image to enlarge
Compensation and SourceAdapt TechnologyOne of the things that naturally become available in this architecture is direct control over the control loop compensation. SMUs have the unusual characteristic that the user's DUT is a part of the control loop. Effectively, we have a control loop that deals with an unknown plant. Analog control loops have a fixed transient response, carefully crafted through the use of active and passive components, that tries to be useful for a wide variety of user loads. This achieves generality by sacrificing optimality. It's impossible for the designer to guess what exact load a user will subject the instrument to. And even if we did know, there would be no practical way to programmatically match the analog-controlled instrument to the load.
A digital loop, of course, allows for considerably more flexibility. We can adjust the bandwidth on the fly or introduce poles and zeros to counteract the effects of reactive loads such as an IC that has bypass capacitors. As an example, Figure 5 shows three possible step responses when driving one volt into a 0.1-ÂµF capacitor. The blue response (labeled "Fast") is similar to what you'd expect from a high-bandwidth SMU designed with sourcing speed in mind. Note the considerable overshoot, which is likely to stress or damage the DUT. Notice also that even though the objective was a fast response, the response is so underdamped that it takes a long time to settle to the desired value.
Figure 5. A fast SMU step response may produce ringing that can damage a device under test. Too much damping (slow response) causes the SMU to take too long to reach its final output, which reduces test throughput. Click on image to enlarge
An SMU could also be designed with a lower bandwidth to be stable on a wider range of loads, and its response would look like the one labeled "Slow" in Figure 5. This one is stable enough, but it still takes over a millisecond to settle within 1% of the setpoint. This will not only increase test times, but also make the output sluggish and incapable of keeping up with sudden transients. The step response labeled "custom" has been tuned to this particular load and as such achieves dramatically better settling times with no overshoot. Custom damping lets the SMU produce an optimized output.
Specialized ADC designI previously mentioned that the ADC on this instrument has some unique requirements. Because we're trying to run a high performance control loop, it's crucial to have a sampling speed that's several times faster than the expected bandwidth of the loop. Latency is also an important consideration, because sampling latency directly translates into lost loop phase, and thus into less usable bandwidth. But on top of that is, after all, a precision DC instrument. We want-high accuracy measurements with about six digits of resolution. Measurements like these require aperture times of close to 20 ms to obtain power-line rejection. So we find ourselves facing conflicting requirements.
Our solution to the problem combines the fast-sampling characteristics of an SAR and the high resolution of sigma-delta-modulated ADCs. We implement the analog signal path using discrete components, and implementing the control logic and filtering in the FPGA. Though the sigma-delta modulator uses a simple comparator for feedback, we add a "residue" SAR ADC next to the comparator, which continuously samples the modulated signal. We can use the FPGA's knowledge of the modulator to demodulate and thus obtain fast "intermediate" samples, which get fed to the control loop. The measurement engine, however, is independent, and filters the output of the sigma-delta in a more traditional way to obtain high precision measurements.
From the control loop's point of view, it's receiving samples at 600 kHz, more than enough to close the loop at the 10-50 kHz bandwidths that are required for a power application. Because those samples come from a sigma-delta modulator, the filtering implicit in the control loop is sufficient to produce outputs that have very high accuracy at low frequencies, almost independently of what kind of DAC we use. In fact, we get better output accuracy and resolution than we would get from a high resolution (18+ bits) DAC because the low-frequency noise of the output is dictated by the characteristics of the ADC. This allows us to use smaller, faster, less linear DACs and skip a lot of the filtering and stabilization that we would usually have to build around those. Since we're always considering both voltage and current, we also automatically get very accurate compliance limits, or clamps, which is uncommon in these instruments. The overall result, of course, is a more compact, more resilient, and -perhaps unexpectedly- more accurate design.
ConclusionWe've explored the unique anatomy of the NI PXIe-4141 four channel precision SMU. We started out by trying to come up with an architecture that would let us pack four channels in a single 3U PXI module and, by challenging the notions of how SMUs are traditionally built, wound up with a design that not only achieves the desired density, but also provides unique functionality that is not available anywhere else in the market. In the end, rather than limit us, the PXI form factor has stimulated a leap forward in Precision DC instrumentation. T&MW
Rolando Ortega holds a bachelor's degree in electrical engineering from ITESM, Queretaro, México. He is currently working on his master's degree in electrical and computer engineering at the University of Texas at Austin. Since joining National Instruments in 2007, he has worked as a digital hardware engineer for the Precision DC group where he was involved in the design of the NI PXI-4130, NI PXI-4132 and NI PXIe-4154 products. He was the lead digital designer for the NI PXIe-4141 SMU described in this article. He is currently a product marketing manager for the NI FlexRIO platform. E-mail: email@example.com