Measure high-voltage logic inputs with your ATE
Peter Sarson, ams- July 10, 2012
Sometimes a test engineer has to use some creativity to overcome challenges. This article details such a situation where a 20 V digital signal from a power management IC had to be measured by an automatic tester with a 6 V digital input capability. In a perfect world, the test system would have the appropriate resources. But, this unusual application required additional resources were not available because the production volume didn't justify it.
One potential solution is to use a high-voltage analog resource for this measurement. This option was discarded due to the extra test time, coding complexity, and additional time needed for debugging and ensuring reliability.
An obvious solution is to use a voltage divider and reduce the voltage by a ratio. Care must be taken because devices with a very low output drive can't overcome the parasitic capacitances of the test system. Therefore the signal needs buffering.
The next step was to determine the type of buffer needed. To accurately test the rise times and fall times of the DUT (device under test), we needed a high-slew-rate buffer. We chose a CFA (current-feedback op amp) because they offer much higher slew rate than VFAs (voltage-feedback op amps). Initially, there were some concerns about using a CFA due to the potential instability that they can sometimes exhibit. See box "CFAs vs. VFAs" at the end of this article for more information.
The next major issue was the voltage range of the operational amplifier; there are many ±5 V and ±15 V op amps available but not ±20 V op amps. We selected the Texas Instruments THS3062 dual current-feedback op amp. This typically runs from a ±15 V supply. If we used this op amp with a ±15 V supply rail, we wouldn't be able to put a 20 V signal through it. To solve this problem we made the supplies +25 V and -5 V with the decoupling capacitors to GND, hence still fulfilling the 30-V supply difference. Figure 1a shows the circuit we used to divide the input voltages down to acceptable levels. Figure 1b shows the circuit used to supply power to the buffer circuit in Figure 1a.
Figure 1a. Click on schematic to enlarge
Figure 1b. Click on schematic to enlarge
Figure 1. (a) A dual current-feedback divides the 20 V DUT signal and (b), a buffer converts DC voltage from +25 V, -5V to ±15 V to power the buffer circuit.
The gain or feedback resistor R37 was chosen to give a gain of 1. The voltage divider, with R42 and R43, was placed on the output. The resistors divide the input signal by a factor of 4. We chose a dual op amp, so we could use the second op amp to buffer the output of the voltage divider to ensure good isolation and drive from the DUT. The OVI (Octal VI) from the tester is used to supply the -5 V and the HVVI (High Voltage VI) the 25 V. The Zener diode is for over-voltage protection.
With the hardware designed for testing flexibility, the next step was to generate the code for implementing the test with a high-voltage digital pin. Because we use a normal digital pin, this is a trivial task except for correlation.
To digitally test this divided 20-V signal, we need to generate a digital pattern but we also need to take into account the rise and fall times but without testing them directly. We solved the problem by putting multiple high-resolution strobe points in the test pattern, for both the high and low cycles and the removal of the strobe points between state switching. Figures 2 and 3 show the timing. As the Design for Test (DFT) was all clock based, we could make a window around the rise and fall time based on a number of system clocks. For this application, the device is specified to fall from 90% to 10% of the programmed output drive within 15 clocks, approximately 1 µs, but in reality the device performed a great deal better. Figure 2 shows that one cycle has a 62.5 ns period with a signal fall time of about 200 ns. IN figure 3, the same signal has a 200 ns rise time.
Figure 2. The signal fall time was approximately 200ns, far better than the maximum 1 µs. Click on image to enlarge
Figure 3. The signal rise time was approximately 200ns, far better than the maximum 1 µs. Click on image to enlarge
Because this is a digital test, Voltage Output Low (Vol) and Voltage Output High (Voh) need to be specified so the tester can be programmed correctly. A 4:1 ratio was used for the voltage divider because the tester needs to be looking for a signal around 5 V. To ensure no yield issues based on instability or other effects, we chose a value of 0.2 V and 4.85 V for Vol and Voh to guarantee an output drive level of 0.8 V and 19.4 V.
Because this is a digital test, this implies a go/no go or pass-fail result. Unfortunately we also needed to guarantee the rise fall times over temperature. Fortunately no adverse effects were seen during temperature characterization and Repeatability and Reproducibility (RR) tests. However, to ensure product quality we guard banded the strobe point by 4 clock periods and we strobed 4 points more than required in order to find any marginal parts. Figure 4 shows the complete strobe cycle and Figure 5 shows the guardbanded strobe points.
Figure 4. A complete strobe cycle shows the off and on pulses with the strobes removed.Click on image to enlarge
Figure 5. The strobe window is guard-banded to 11 strobes. Click on image to enlarge
The circuitry on the load board must also be tested before each production run. During program load each of the amplifier banks are checked to ensure they have a gain of 0.25. If these checks fail, production cannot continue until the board has been repaired. This procedure ensures that bad product cannot be shipped due to faulty boards and false passes.
Because we're established a production history for this technique, we can reuse it with confidence. We have implemented this solution successfully on multiple products to test high-voltage signals. Once the volume of these products reaches a specified level, consideration we will give consideration to purchasing additional tester resources.
With some additional foresight a complicated and unreliable test solution can be avoided by adding some additional circuitry to a loadboard to test high voltage digital signals. If done correctly this solution can be stored as an IP Block and reused. TMW
For further reading
Jung, Walt "Op Amp Applications Handbook,".
Mancini, Ron, "Op Amps For Everyone."
Peter Sarson is the test development manager for ams (formerly Austria Micosystems) Full Service Foundry businessunit. He received his BEng (Hons) from Sheffield University, UK, in 1998 and his chartered engineer status from the Institution of Engineering and Technology (formerly the Institution of Electrical Engineers) in 2003. He has worked in automated test engineering for 11 years.
CFAs Versus VFAs and Selection of the Feedback Resistor
A current-feedback amplifier's inverting input is sensitive to current rather than voltage as in a conventional amplifier. The feedback resistor determines stability and affects closed-loop bandwidth, so it must be selected very carefully. Most CFA IC manufacturers spend a great deal of time and effort selecting the feedback resistor (RF). They measure each non-inverting gain with several different feedback resistors to gather data. Then they pick a value of RF that yields stable operation with acceptable peaking; that value of RF is recommended on the data sheet for that specific gain. This procedure is repeated for several different gains in anticipation of the gains their customer's applications require (often G = 1, 2, or 5). When the value of RF or the gain is changed from the values recommended on the data sheet, bandwidth and/or stability is affected.
As RF is decreased, stability is decreased, and when RF goes to zero the circuit becomes unstable. Conversely, as RF is increased stability increases, but bandwidth decreases. Stray capacitance on the inverting input node or across the feedback resistor always leads to peaking, usually to ringing, and sometimes to oscillations. Bread boarding and lab testing are a must with CFAs. The CFA performance can be greatly improved with good layout, good decoupling capacitors, and low inductance components.